As basic electronics building blocks, field-effect transistor (FETs) are widely used in both logic and memory chips. A typical FET is a three-terminal device consisting of source (S), drain (D), and gate (G) contacts. In operation, conductivity between the S and D contacts is modulated by applying a voltage or an applied electric field through the G contact, resulting in ON and OFF states. Although FETs have evolved structurally from early planar geometries to their current three-dimensional (3D) geometries and have continually shrunk in size, the basic operating principal remains the same. The structural changes and shrinkage have led to ever greater fabrication complexity, and ultimately to challenges in gate fabrication and doping control.
Various new technologies, such as fin field-effect transistors (FinFETs) and tunnel-FETs have been developed in recent years to enable the continuation of Moore's law. Other types of FETs are also being explored as alternatives, such as semiconductor nanowire (SNW) based FETs, FETs comprised of two-dimensional (2D) materials, and FETs with multiple independent gates or gates with embedded ferroelectric material. However, the above-referenced technologies may not provide a clear pathway for eliminating gating complexity or avoiding difficulties with doping control. Furthermore, a viable rival technology does not currently exist.